Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
Advantages of Using CMOS - ppt video online download
NB7V52M - D Flip Flop, 1.8 V / 2.5 V Differential, with Reset and CML Outputs
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
adding reset function to D Flip FLOP | Forum for Electronics
Current-Mode-Logic (CML) Latch | EveryNano Counts
Electronics | Free Full-Text | High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler
Electronics | Free Full-Text | 0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
MC74VHC74 datasheet - Dual D Flip-Flop with Set and Reset. The MC74VHC74
DFF-based CMOS clock divider. | Download Scientific Diagram
ECEN620: Network Theory Broadband Circuit Design Fall 2022
adding reset function to D Flip FLOP | Forum for Electronics
A Dynamic Current Mode D-Flipflop for High Speed Application
Circuit configuration of the RTD/HBT MOBILE-based NRZ D-flip flop. | Download Scientific Diagram
Figure 1 from A 45 mW RTD/HBT MOBILE D-Flip Flop IC Operating up to 32 Gb/s | Semantic Scholar
Part 01: Proposal and Overview. Dual Modulus Prescaler Using Current Mode Logic Goals 2.5 GHz Operation 8/9 Dual Modulus 0.18uM BSIM 3 Model. - ppt download
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool
High speed CML latch using active inductor in 0.18μm CMOS technology | Semantic Scholar
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
