Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
High Speed Digital Blocks
Figure 1 from High-frequency CML clock dividers in 0.13-/spl mu/m CMOS operating up to 38 GHz | Semantic Scholar
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Figure 1 from A 45 mW RTD/HBT MOBILE D-Flip Flop IC Operating up to 32 Gb/s | Semantic Scholar
Analysis and Design of High-Speed CMOS Frequency Dividers
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
adding reset function to D Flip FLOP | Forum for Electronics
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
Electronics | Free Full-Text | 0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
PPT - Advantages of Using CMOS PowerPoint Presentation, free download - ID:3409185
A Dynamic Current Mode D-Flipflop for High Speed Application
![PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/a9f1b39596e7f08405b62eebe623914a1e5c78d1/2-Figure2-1.png "PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar")
PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar
Circuit configuration of the CML-type SR-latch circuit a Circuit... | Download Scientific Diagram
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
PDF) Novel Differential-Mode RTD/HBT MOBILE-based D-Flip Flop IC
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
